An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range

@article{Bannon2014An1B,
  title={An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range},
  author={Alan Bannon and Christopher P. Hurrell and Derek Hummerston and Colin Lyden},
  journal={2014 Symposium on VLSI Circuits Digest of Technical Papers},
  year={2014},
  pages={1-2}
}
This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high… CONTINUE READING
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