An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS

Abstract

This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC). The proposed hybrid architecture combines the design benefits of different ADC structures to achieve a high conversion rate and accuracy with good power efficiency. The design employs multiple… (More)
DOI: 10.1109/JSSC.2016.2522762

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