An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS

@article{Inerfield2014An11,
  title={An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS},
  author={Michael Inerfield and Abhishek Kamath and Feng Su and Jason Hu and Xinyu Yu and Victor Fong and Omar Alnaggar and Fang Lin and Tom W. Kwan},
  journal={2014 Symposium on VLSI Circuits Digest of Technical Papers},
  year={2014},
  pages={1-2}
}
Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power <; 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It uses a unique dual-reference, dual unit-cap architecture with a regulated DAC switch, providing a 2Vppd… CONTINUE READING

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