An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS

@article{Sumesaglam2014An1R,
  title={An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS},
  author={Taner Sumesaglam},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2014},
  volume={61},
  pages={219-223}
}
A receiver circuit employing a dynamic linear equalization technique is presented. The new circuit method removes the traditional continuous-time linear equalizer (CTLE) and builds equalization into strong-arm latches (SALs). Fabricated in a 22-nm CMOS technology, the receiver's performance is experimentally verified at 11 Gb/s with better than bit error rate 10-12 at 0.17 mW/Gb/s power efficiency, which advances the state of the art. The power efficiency is 55% better than the CTLE alternative… CONTINUE READING
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Dynamic linear equaliser circuit

  • T. Sumesaglam
  • Electron. Lett., vol. 47, no. 11, pp. 642–644…
  • 2011
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