• Corpus ID: 23745877

Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation

  title={Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation},
  author={Marie Nguyen and James C. Hoe},
Dynamic partial reconfiguration (DPR) allows one region of an field-programmable gate array (FPGA) fabric to be reconfigured without affecting the operations on the rest of the fabric. [] Key Method To overcome this inefficiency, we devised an "amorphous" DPR technique that is compatible with current device and tool support but does not require the DPR partition boundaries to be a priori fixed.
2 Citations

Figures and Tables from this paper

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

This article proposes a tool, called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs, and proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain.

Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs

This article implements the AES with three different key lengths and different block cipher modes using High-Level Synthesis (HLS), and shows a possible occurrence to implement partial reconfiguration of multi-mode AES crypto algorithms in different configurations of AP SoCs during run-time.



Dynamic scheduling of tasks on partially reconfigurable FPGAs

It is proposed that a subset of the tasks executing on the FPGA be rearranged when to do so allows the next pending task to be processed sooner, and methods are described and evaluated for overcoming the NP-hard problems of identifying feasible rearrangements and scheduling the rearranger when moving tasks are reloaded from off-chip.

Configuration relocation and defragmentation for run-time reconfigurable computing

Hardware solutions to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA, as well as software algorithms for controlling this hardware are presented.

Hierarchical reconfiguration of FPGAs

For complex systems where many modules have common parts or where modules can share components, it is shown that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to thenumber of modules and submodules.

Go Ahead: A Partial Reconfiguration Framework

The tool Go Ahead is introduced that is able to implement run-time reconfigurable systems for all recent Xilinx FPGAs and provides a scripting interface and all features can be accessed remotely.

Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC

The proposed method tries to reduce fragmentation during placement itself, which means that not only the reconfigurable space is utilized more efficiently, but the total schedule length is also reduced, that is, hardware tasks complete faster.

Placing partially reconfigurable stream processing applications on FPGAs

This work defines a placement method based on transforming the inherent two dimensional structure of the FPGA into a one dimensional string and employing string matching, which is suited to compute a module placement over multiple chained reconfigurable regions.

Runtime Task Mapping Based on Hardware Configuration Reuse

The obtained result shows up to 45\% performance gain by reusing the hardware configurations as suggested by the proposed heuristic, compared to well-known approaches from the state-of-the-art, which do not take into consideration the hardware configuration reuse.

Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures

The proposed scalable BRAM memory management architecture adaptively manages these dynamic memory requirements and balances the buffer memory over several PEs to reduce the total memory required, compared to the worst-case memory footprint for all PEs.

Online scheduling for block-partitioned reconfigurable devices

This paper proposes an online scheduling system that allocates tasks to a block-partitioned reconfigurable device that can have different widths, which allows the matching of the computational resources with the task requirements.

FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack

It is shown that FPGA cloud compute resources can easily outperform virtual machines, while the system's virtualization and abstraction significantly reduces design iteration time and design complexity.