Allocation of FPGA DSP-macros in multi-process high-level synthesis systems

@article{Schafer2014AllocationOF,
  title={Allocation of FPGA DSP-macros in multi-process high-level synthesis systems},
  author={Benjamin Carrion Schafer},
  journal={2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)},
  year={2014},
  pages={616-621}
}
High-Level Synthesis (HLS) is a single process synthesis method that has shown to produce very good results compared to hand coded RTL, especially for DSP-related applications. At the same time FPGAs are reaching capacities that allow entire systems to be implemented on them. Most of these systems are also DSP-related and make intensive use of the FPGAs' embedded hardmacros (e.g. DSP-blocks). This works presents a method to efficiently allocate DSP-macros in multi-process systems created using… CONTINUE READING

Similar Papers

Loading similar papers…