Allocation and optimization of Post-silicon tunable buffers in TSV based heterogeneous 3D ICs

Abstract

Through-silicon via (TSV) based 3D IC design is a promising solution to reducing the length of interconnects and improving the power and speed. However, when heterogeneous dies are stacked together to form a 3D IC, a considerable timing discrepancy among the layers could happen since the devices in different layers might have been affected quite differently… (More)

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