All-Copper Chip-to-Substrate Interconnects Part II . Modeling and Design

@inproceedings{He2008AllCopperCI,
  title={All-Copper Chip-to-Substrate Interconnects Part II . Modeling and Design},
  author={Ate He and Tyler Osborn and Sue Allen and Paul A. Kohl},
  year={2008}
}
A fabrication technique involving electroand electroless copper deposition was used to produce all-copper chip-to-substrate interconnects. This process electrolessly joins copper pillars, followed by annealing at 180°C. The process is tolerant to in-plane and through-plane misalignment and height variations. The mechanical compliance and electrical performance of copper-pillar chip-to-substrate interconnects is modeled in this paper. The elastic, thermomechanical behavior and electrical… CONTINUE READING