All-CMOS High-Speed CML Gates with Active Shunt-Peaking

@article{Kalantari2007AllCMOSHC,
  title={All-CMOS High-Speed CML Gates with Active Shunt-Peaking},
  author={Nader Kalantari and Michael M. Green},
  journal={2007 IEEE International Symposium on Circuits and Systems},
  year={2007},
  pages={2554-2557}
}
The design of CMOS current-mode logic (CML) logic gates is discussed. A novel CML transistor-only topology that realizes an active inductive load is presented. This topology makes use of thicker oxide transistors often available in standard CMOS processes and an additional, higher, supply voltage that does not conduct any dc current. It is shown by simulation results that this topology provides favorable dc biasing compared to existing techniques while exhibiting better performance. 

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