Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure

@article{Ren2008AlgorithmsFS,
  title={Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure},
  author={H. Ren and S. Dutt},
  journal={2008 IEEE/ACM International Conference on Computer-Aided Design},
  year={2008},
  pages={93-100}
}
  • H. Ren, S. Dutt
  • Published 2008
  • Computer Science
  • 2008 IEEE/ACM International Conference on Computer-Aided Design
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay under area constraints by simultaneously considering the benefits and costs of all transforms (as opposed to considering them sequentially after applying each transform). The circuit transforms we employ include, but are not limited to, incremental placement, two types of buffer insertion, cell resizing and cell… Expand
A Methodology for Cell Merging Circuit Transformation on Post- placement High Speed Design
TLDR
A localize circuit transformation algorithm to further optimize the post-placement netlist by replacing a small group of cells that are placed close to each other with a functional equivalent standard cell available in the technology library. Expand
Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous $V_{dd}$, $V_{th}$ Assignments, Gate Sizing, and Placement
  • H. Ren, S. Dutt
  • Engineering, Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2011
TLDR
An approach is developed that along with the option selection process can simultaneously determine the voltage islands needed, as well as satisfy all given constraints, that reduces power by an additional amount of up to 19%, and an average of 16%. Expand
Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm
TLDR
A timing-driven discrete cell-sizing algorithm that can address total cell size and/or leakage power constraints, and can obtain near-optimal solutions in a time-efficient manner is proposed. Expand
On Incremental Component Implementation Selection in System Synthesis
  • S. Ghiasi
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2010
TLDR
This paper presents a methodology for incrementally solving component implementation selection problem (CISP) in face of local or non-local perturbations, and develops an algorithm that maintains both validity and optimality of a solution under incremental changes. Expand
An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs
TLDR
This work proposes an interactive methodology to perform physical synthesis in the pre-placement stage of the FPGA timing closure flow and evaluates the effectiveness and performance of the proposed approach on a large set of industrial designs. Expand
Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor
  • R. S. Shelar, M. Patyra
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2013
TLDR
An extensive study carried out on RTL-to-layout synthesized blocks in a 45-nm technology core shows that the interconnects in these blocks account for 30% of the cycle time, on an average, on the worst internal timing paths and contribute nearly one-third to the power dissipation. Expand
Selection of Multiple SNPs in Case-Control Association Study Based on a Discretized Network Flow Approach ?
Recent large scale genome-wide association studies have been considered to hold promise for unraveling the genetic etiology of complex diseases. It becomes possible now to use these data to assessExpand
New Algorithmic Techniques for Complex EDA Problems

References

SHOWING 1-10 OF 16 REFERENCES
Transformational placement and synthesis
TLDR
Experimental results indicate that the proposed approach creates an efficient converging design flow that eliminates placement and synthesis iteration and results in timing improvements, and maintains other global placement measures such as wire congestion and wire length. Expand
A Methodology and Algorithms for Post-Placement Delay Optimization
TLDR
A placement-intelligent resynthesis methodology and optimization algorithms to meet post-layout timing constraints while at the same time reducing the interconnect congestion is presented. Expand
Combining technology mapping with post-placement resynthesis for performance optimization
TLDR
An innovative two-phase approach which combines technology mapping with logic resynthesis for minimizing the post-placement delays when compared with SIS-1.2. Expand
Timing driven gate duplication
TLDR
This paper addresses the problem of delay optimization by gate duplication by presenting an algorithm that traverses the network from primary outputs to primary inputs in topologically sorted order evaluating tuples at the input pins of gates. Expand
A Network-Flow Based Cell Sizing Algorithm
We propose a timing-driven discrete cellsizing algorithm that can incorporate total cell size constraints. We model cell sizing as a min-cost network flow problem. In the network flow graph,Expand
Buffer placement in distributed RC-tree networks for minimal Elmore delay
TLDR
An algorithm is presented for choosing the buffer positions for a wiring tree such that the Elmore delay is minimal, and an extension of the basic algorithm allows minimization of the number of buffers as a secondary objective. Expand
Gate sizing for constrained delay/power/area optimization
  • O. Coudert
  • Computer Science, Engineering
  • IEEE Trans. Very Large Scale Integr. Syst.
  • 1997
TLDR
This work discussed here a gate sizing algorithm (GS), and showed how it is used to achieve constrained optimization, and how it can be applied on large circuits within a reasonable CPU time. Expand
A network-flow approach to timing-driven incremental placement for ASICs
TLDR
Wepresent anovel incremental placement methodology called FlowPlace for significantly reducing critical pathdelays of placed standard-cell circuits and extracting performance improvements from a performanceoptimized layout. Expand
Timing-driven placement using design hierarchy guided constraint generation
TLDR
A novel slack assignment approach is described as well as its application on delay budgeting with design hierarchy information, and the proposed timing-driven placement flow is implemented into a placement tool named Dragon (timing-driven mode), and evaluated using an industrial place and route flow. Expand
Interleaving buffer insertion and transistor sizing into a single optimization
TLDR
The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area delay tradeoff curves shown in this paper. Expand
...
1
2
...