• Corpus ID: 60936226

Algorithms for VLSI design automation

  title={Algorithms for VLSI design automation},
  author={Sabih H. Gerez},
From the Publisher: Modern microprocessors such as Intel's Pentium chip typically contain millions of transitors. Known generically as Very Large-Scale Integrated (VLSI) systems, the chips have a scale and complexity that has necessitated the development of CAD tools to automate their design. This book focuses on the algorithms which are the building blocks of the design automation software which generates the layout of VLSI circuits. One of the first books on the subject, this guide covers… 

Computer aided partitioning for design of parallel testable VLSI systems

An automated VLSI design tool for partitioning combinational CMOS circuits that can create parallel testable V LSI circuits, is developed and discussed and can optimize the design constraints of test time and hardware overhead for design-for-testability (DFT).

Algorithms for CAD Tools VLSI Design

The partitioning methodology proved to be very useful in solving the VLSI design automation problems occurring in every stage of the IC design process, but the size and the complexity of the V LSI design has increased over time, hence some of the problems can be solved using partitioning techniques.

Automatic generation of digital cell libraries

This paper presents cell design flow - CDF, a tool for automatic generation of digital cell libraries. It is able to synthesize physical layouts of logic cells from truth table descriptions or

Layout Problem Optimization in VLSI Circuits Using Genetic Algorithm

A Genetic Algorithm based approach is proposed to reduce the chip area by means of effective placement of the modules in very-large-scale-integration to produce effective placement.


This paper presents a new algorithm for transistor placement of nondual cells. These cells do not have complementary series-parallel planes. The solution consists of an integration of 3 other

A Genetic Approach for Area Reduction in VLSI Layout

Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit. Integrated

Rectangle Placement for VLSI Testing

This work used constraint programming (CP) with additional heuristics, including sophisticated variable and value orderings, to produce floorplans for real test-sites and the solution is successfully used in production by test-site designers.

FPGA implementation of a new parallel routing algorithm

  • K. FatimaR. Rao
  • Computer Science
    TENCON 2008 - 2008 IEEE Region 10 Conference
  • 2008
A new parallel processing wire routing algorithm, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip or a PCB, and yields orders of magnitude speedups over software implementation.

Incremental Design Methodology for Multimillion-gate Fpgas

The results show that the incremental design methodology is in orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing too much quality.

A novel ultra-fast heuristic for VLSI CAD steiner trees

A fast Steiner tree construction algorithm, which is 3-180 times faster for 10-300 point Steiner trees, and within 2.5% of the length of the Batched-1-Steiner tree, is proposed.



Modern VLSI design - a systems approach

1. Digital Systems and VLSI, 2. Analysis and Synthesis Tools, and Design Examples.

Computation structures

From the Publisher: Computation Structures integrates thorough coverage of digital logic design with a comprehensive presentation of computer architecture. It contains a wealth of information for

The Magic VLSI Layout System

Magic is a new IC layout system that includes several facilities traditionally contained in separate batch-processing programs. Magic incorporates expertise about design rules, connectivity, and

Parallel algorithms for VLSI computer-aided design

This text discusses the design and use of practical parallel algorithms for solving problems in a growing application area whose computational requirements are enormous - VLSI CAD applications.

VLSI Chip Design with the Hardware Description Language VERILOG

  • U. Golze
  • Computer Science, Materials Science
    Springer Berlin Heidelberg
  • 1996
Design of VLSI Circuits.- Design of VLSI Circuits.- RISC Architectures.- RISC Architectures.- Short Introduction to VERILOG.- Short Introduction to VERILOG.- External Specification of Behavior.-

Formal hardware verification methods: A survey

  • Aarti Gupta
  • Computer Science
    Formal Methods Syst. Des.
  • 1992
This article presents a classification framework for the various methods, based on the forms of the specification, the implementation, and the proff method, to better highlight the relationships and interactions between seemingly different approaches.

High-level algorithm and architecture transformations for DSP synthesis

  • K. Parhi
  • Computer Science
    J. VLSI Signal Process.
  • 1995
This survey paper reviews numerous high-level transformation techniques which can be applied at the algorithm or the architecture level to improve the performance of digital signal and image

Vhdl: A Logic Synthesis Approach

VHDL: A Logic Synthesis Approach is specifically targeted at this audience and is also essential reading for engineers wishing to use the more basic manual VHDL techniques.

Power minimization in IC design: principles and applications

An in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems is presented and the many issues facing designers at architectural, logical, and physical levels of design abstraction are described.

Cameleon, a Process Tolerant Symbolic Layout System

CAMELEON is a symbolic layout system, suited for industrial designs, delivering layouts that can bear comparison with (orthogonal) manual layouts. The Technology Description Language (TDL),