Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes

@article{Voinigescu2005AlgorithmicDM,
  title={Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes},
  author={Sorin P. Voinigescu and Timothy O. Dickson and Theodoros Chalvatzis and Altan Hazneci and Ekaterina Laskin and Rudy Beerkens and Imran Khalid and Edward S. Rogers},
  journal={Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.},
  year={2005},
  pages={111-118}
}
This paper presents an analysis of sub-2.5-V topologies and design methodologies for SiGe BiCMOS and sub-90nm CMOS building blocks to be used in the next generation of 40-100 Gb/s wireline transceivers. Examples of optimal designs for 40-80Gb/s broadband low-noise input comparators, low-voltage high-speed MOS- and BiCMOS CML logic gates, 30-100 GHz low-noise oscillators, and 40/80 GHz output drivers with wave shape control are provided. 
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