Corpus ID: 117489957

Algorithmic Reduction And Optimization Of Logic Circuit In Area And Power Tradeoffs’ With The Help Of Binary Decision Diagram

@article{Kaur2013AlgorithmicRA,
  title={Algorithmic Reduction And Optimization Of Logic Circuit In Area And Power Tradeoffs’ With The Help Of Binary Decision Diagram},
  author={Sukhmanjeet Kaur and M. Bansal},
  journal={International journal of engineering research and technology},
  year={2013},
  volume={2}
}
This paper presents an algorithmic technique based on hybridizing Symbolic Manipulation Techniques based on BDDs with more traditional explicit solving algorithms. Boolean functions can be graphically manipulated to reduce the number of nodes, hence the area, when implemented as Binary decision diagrams. So here, ordering of BDD nodes plays a very important role. Most of the algorithms for variable ordering of OBDD have focus on area minimization. Hence, for minimizing the power consumption… Expand

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