Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications

@article{Fujita2011AdvancedCE,
  title={Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications},
  author={Kazuhide Fujita and Yoshiya Torii and Mitsuaki Hori and J. Oh and Lucian Shifren and Pushkar Ranade and Mina Nakagawa and K. Okabe and Takao Miyake and Kazuo Ohkoshi and M. Kuramae and Toshifumi Mori and T. Tsuruta and Sally E Thompson and T. Ema},
  journal={2011 International Electron Devices Meeting},
  year={2011},
  pages={32.3.1-32.3.4}
}
We have achieved aggressive reduction of V<inf>T</inf> variation and V<inf>DD-min</inf> by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V<inf>T</inf> variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV… CONTINUE READING
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