Adding instruction cache effect to schedulability analysis of preemptive real-time systems

@inproceedings{BusquetsMataix1996AddingIC,
  title={Adding instruction cache effect to schedulability analysis of preemptive real-time systems},
  author={Jos{\'e} V. Busquets-Mataix and Juan Jos{\'e} Serrano and Rafael Ors Carot and Pedro J. Gil and Andy J. Wellings},
  booktitle={IEEE Real Time Technology and Applications Symposium},
  year={1996}
}
Cache memories are commonly avoided in real-time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. This paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis… CONTINUE READING
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