Adder circuits using symmetric and asymmetric FinFETs


In this paper we are examining different configurations and circuit topologies for adder circuits using both symmetric and asymmetric work-function FinFET transistors. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50% respectively compared to results in the literature. For the 14 transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29% respectively compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achieves reduction in leakage by 85% with a small degradation of 7% in delay. All simulations are based on 25nm FinFET technology using the University of Florida UFDG model.

11 Figures and Tables

Cite this paper

@article{Moshgelani2013AdderCU, title={Adder circuits using symmetric and asymmetric FinFETs}, author={Farid Moshgelani and Dhamin Al-Khalili and Come Rozon}, journal={2013 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA)}, year={2013}, pages={23-26} }