Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures

Abstract

The increasing wire delay constraints in deep sub-micron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power consumption, area overhead and performance of the entire NoC is influenced by the router buffers, research efforts have targeted optimized router buffer design. In this paper, we propose… (More)
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@article{Kodi2009AdaptiveIL, title={Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures}, author={Avinash Karanth Kodi and Ashwini Sarathy and Ahmed Louri and Janet Roveda}, journal={2009 Asia and South Pacific Design Automation Conference}, year={2009}, pages={1-6} }