Adaptive Power Optimization of On-chip SNUCA Cache on Tiled Chip Multicore Architecture Using Remap Policy

@article{Mandke2011AdaptivePO,
  title={Adaptive Power Optimization of On-chip SNUCA Cache on Tiled Chip Multicore Architecture Using Remap Policy},
  author={Aparna Mandke and Bharadwaj S. Amrutur and Y. N. Srikant},
  journal={2011 Second Workshop on Architecture and Multi-Core Applications (wamca 2011)},
  year={2011},
  pages={12-17}
}
Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage powerconsumption of on-chip caches has already become a major power consuming component of the memory subsystem.  We propose to reduce leakage powerconsumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unusedcache slices. A cache slice in a tile includes all cache… CONTINUE READING
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Adaptive Power Optimization of OnChip

  • A. Mandke, A. Bharadwaj, Y. N. Srikant
  • SNUCA Cache on Tiled CMP using Remap Policy. http…
  • 2011
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