A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing
This paper presents the design of a low power, variable resolution, successive approximation analog-to-digital converter (ADC). This converter will be the base cell in an array of 100 converters intended for use in a neuro-prosthetic implant. The ADC resolution can be varied from 3 to 8 bits in 1 bit steps. Offset cancellation is required for /spl ges/ 7 bit resolution. The power consumption of the base ADC ranges from 0.5/spl mu/W at 3 bit resolution to 0.9 /spl mu/W at 6 bits and to 4 /spl mu/W at 8 bits whilst maintaining INL and DNL < 0.5 bit at 100 kS/s.