## A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing

- Salwa Mostafa, Wenchao Qu, Syed Kamrul Islam, Mohamed Mahfouz
- 2010 IEEE Computer Society Annual Symposium on…
- 2010

1 Excerpt

- Published 2005 in Proceedings of the 2005 European Conference on…

This paper presents the design of a low power, variable resolution, successive approximation analog-to-digital converter (ADC). This converter will be the base cell in an array of 100 converters intended for use in a neuro-prosthetic implant. The ADC resolution can be varied from 3 to 8 bits in 1 bit steps. Offset cancellation is required for /spl ges/ 7 bit resolution. The power consumption of the base ADC ranges from 0.5/spl mu/W at 3 bit resolution to 0.9 /spl mu/W at 6 bits and to 4 /spl mu/W at 8 bits whilst maintaining INL and DNL < 0.5 bit at 100 kS/s.

@article{ODriscoll2005AdaptiveAD,
title={Adaptive ADC design for neuro-prosthetic interfaces: base ADC cell},
author={Stephen O'Driscoll and T. H. Meng},
journal={Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.},
year={2005},
volume={1},
pages={I/301-I/304 vol. 1}
}