Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design

@article{Keppens2003ActiveareasegmentationT,
  title={Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design},
  author={Bart Keppens and M.P.J. Mergens and John Armer and P. C. Jozwiak and Gerry Taylor and R. Mohn and Cong Son Trinh and C. Russ and K. Verhaege and F. De Ranter},
  journal={2003 Electrical Overstress/Electrostatic Discharge Symposium},
  year={2003},
  pages={1-9}
}
This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13 um and a 0.18 um CMOS technology obtaining HBM ESD capability of up to 8.6 V/um2. 
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