Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver

@article{Sharma2005AccuratePO,
  title={Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver},
  author={Ajit Sharma and Patrick Birrer and Sasi Kumar Arunachalam and Chenggang Xu and Terri S. Fiez and Kartikeya Mayaram},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2005},
  volume={13},
  pages={843-851}
}
This paper presents an automated methodology for calibrating the doping profile and accurately predicting substrate parasitics with boundary element solvers. The technique requires fabrication of only a few test structures and results in an accurate three-layered approximation of a heavily doped epitaxial silicon substrate. Using this approximation, the extracted substrate resistances are accurate to within 10% of measurements. The calibrated parasitic extractor results in good agreement… CONTINUE READING

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