Accellera Verilog + + Extension assertion construct Requirements Contact

@inproceedings{Foster2001AccelleraV,
  title={Accellera Verilog + + Extension assertion construct Requirements Contact},
  author={Harry D. Foster and Harry},
  year={2001}
}
Extension assertion construct Justification: The question arises whether extension assertion constructs are necessary. After all, many Hardware Verification Languages (HVLs) provide powerful language features that can be used to describe correct temporal behavior. These HVLs can be used for data generation and results analysis thru temporal specification… CONTINUE READING