Accelerating multiple alignment on FPGA with a high-level hardware description language

  • O. V. Medvedev
  • Published 2011 in
    2011 7th Central and Eastern European Software…

Abstract

The paper describes an experience of creating a hardware implementation of a pairwise sequence alignment algorithm in a high-level hardware description language. The implementation is created to be run on an FPGA with a high latency interface to a PC (ethernet). Thus, a lot of control logic is implemented in hardware together with the main pipeline. We use… (More)

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Cite this paper

@article{Medvedev2011AcceleratingMA, title={Accelerating multiple alignment on FPGA with a high-level hardware description language}, author={O. V. Medvedev}, journal={2011 7th Central and Eastern European Software Engineering Conference (CEE-SECR)}, year={2011}, pages={1-7} }