Accelerated processing delay optimization in hierarchical networks using low cost hardware

@article{Ulbricht2016AcceleratedPD,
  title={Accelerated processing delay optimization in hierarchical networks using low cost hardware},
  author={Marian Ulbricht and Jens Wagner},
  journal={2016 10th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP)},
  year={2016},
  pages={1-6}
}
Delay optimization is a today's topic. Delay is an important quality of service (QoS) parameter. In this paper, we present a technique that uses IP-addresses to encode the way a packet passes through the network without using a lookup table as well as a hardware accelerator to use this encoded information. Using this method, the time a packet that is delayed in the router is decreased dramatically, and the time to calculate the routing information is predictable. We show in simulation that this… CONTINUE READING

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