Accelerate FPGA routing with parallel recursive partitioning

@article{Shen2015AccelerateFR,
  title={Accelerate FPGA routing with parallel recursive partitioning},
  author={Minghua Shen and Guojie Luo},
  journal={2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  year={2015},
  pages={118-125}
}
FPGA routing is a time-consuming step in the EDA design flow. In this paper we present a coarse-grained recursive partitioning approach to exploit parallelism. The basic idea is to partition the nets into three subsets, where the first subset and the other two subsets consist of potentially conflicting nets and potentially conflicting-free nets, respectively. The two potentially conflicting-free subsets are routed in parallel after the first subset is routed. And all subsets are recursively… CONTINUE READING
11 Citations
3 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 11 extracted citations

References

Publications referenced by this paper.
Showing 1-3 of 3 references

Similar Papers

Loading similar papers…