ATPG for Reversible Circuits using Technology-Related Fault Models

  title={ATPG for Reversible Circuits using Technology-Related Fault Models},
  author={Jeff S. Allen and Jacob D. Biamonte and Marek A. Perkowski},
We address the problem of test set generation and test set reduction, to first detect, and later localize faults occurring in reversible circuits. Reversible Computation has high promise of low power consumption. Some new fault models are first presented here. An explanation of the new fault models is made based on a physical realization representing the state of the art in the reversible CMOS circuit technology. Evidence is then presented showing that the fault models presented in the current… CONTINUE READING


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Testing a Quantum Computer

  • J. Biamonte, M. Perkowski
  • Proceedings of, KAIS, Workshop on Quantum…
  • 2004
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