ATGPS using real value logic simulation

  • Goro Suzuki
  • Published 2014 in
    2014 12th IEEE International Conference on Solid…

Abstract

In terms of Automatic Test Pattern Generation System, we proposed a new algorithm which employs real value logic simulation, but gate output value calculation method is quite different from Cheng and Agrawal's in order to realize high fault coverage and process acceleration. Moreover, we implemented our algorithm on parallel processor and could yield high speed processing. Compared with Cheng and Agrawal algorithm, acceleration is about 4× with 100(%) fault coverage. And acceleration is more than 5× using parallel processor moreover.

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Cite this paper

@article{Suzuki2014ATGPSUR, title={ATGPS using real value logic simulation}, author={Goro Suzuki}, journal={2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)}, year={2014}, pages={1-4} }