ASIC implementation of high speed pipelined DDR SDRAM controller

@article{Reddy2014ASICIO,
  title={ASIC implementation of high speed pipelined DDR SDRAM controller},
  author={Nadiminti Satish Reddy and Ganesh Chokkakula and Bhumarapu Devendra and K. Sivasankaran},
  journal={International Conference on Information Communication and Embedded Systems (ICICES2014)},
  year={2014},
  pages={1-5}
}
Modern real-time embedded system must support multiple concurrently running applications. Double Data Rate Synchronous DRAM (DDR SDRAM) became mainstream choice in designing memories due to its burst access, speed and pipeline features. Synchronous dynamic access memory is designed to support DDR transferring. To achieve the correctness of different applications and system work as to be intended, the memory controller must be configured with pipelined design for multiple operations without… CONTINUE READING