ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS

@article{Mohan2020ASICAI,
  title={ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS},
  author={Prashanth Mohan and Wen Wang and Bernhard Jungk and Ruben Niederhagen and Jakub Szefer and Ken Mai},
  journal={2020 IEEE 38th International Conference on Computer Design (ICCD)},
  year={2020},
  pages={656-662}
}
  • P. MohanWen Wang K. Mai
  • Published 1 October 2020
  • Computer Science
  • 2020 IEEE 38th International Conference on Computer Design (ICCD)
This paper presents the first 28 nm ASIC implementation of an accelerator for the post-quantum digital signature scheme XMSS. In particular, this paper presents an architecture for a novel, pipelined XMSS Leaf accelerator for accelerating the most compute-intensive step in the XMSS algorithm. This paper then presents the ASIC designs for both an existing non-pipelined accelerator architecture and the novel, pipelined XMSS Leaf accelerator. In addition, the performance of the 28 nm ASIC is… 

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