AOS: Adaptive overwrite scheme for energy-efficient MLC STT-RAM cache

@article{Chen2016AOSAO,
  title={AOS: Adaptive overwrite scheme for energy-efficient MLC STT-RAM cache},
  author={Xunchao Chen and Navid Khoshavi and Jian Zhou and Dan Huang and Ronald F. DeMara and Jun Wang and Wujie Wen and Yiran Chen},
  journal={2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)},
  year={2016},
  pages={1-6}
}
Spin-Transfer Torque Random Access Memory (STT-RAM) has been identified as an advantageous candidate for on-chip memory technology due to its high density and ultra low leakage power. Recent research progress in Magnetic Tunneling Junction (MTJ) devices has developed Multi-Level Cell (MLC) STT-RAM to further enhance cell density. To avoid the write disturbance in MLC strategy, data stored in the soft bit must be restored back immediately after the hard bit switching is completed. However… CONTINUE READING
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