ADC-Based Backplane Receiver Design-Space Exploration

  title={ADC-Based Backplane Receiver Design-Space Exploration},
  author={Hayun Chung and Gu-Yeon Wei},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
Demand for higher throughput backplane communications, coupled with a desire for design portability and flexibility, has led to high-speed backplane receivers that use front-end analog-to-digital converters (ADCs) and digital equalization. Unfortunately, power and complexity of such receivers can be high and require careful design. This paper presents a parameterized ADC-based backplane receiver model that facilitates design-space exploration to optimize the tradeoffs between power and… CONTINUE READING


Publications citing this paper.

ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2018
View 6 Excerpts
Highly Influenced


Publications referenced by this paper.
Showing 1-10 of 23 references

Predictive Technology Model [Online].

View 1 Excerpt

Equalizer design and performance trade-offs in ADC-based serial links

IEEE Custom Integrated Circuits Conference 2010 • 2010
View 1 Excerpt

A 500 mW digitally calibrated AFE in 65 nm CMOS for 10 Gb/s serial links over backplane and multimode fiber

J. Cao, B. Zhang, +10 authors A. Momtaz
Proc. IEEE ISSCC, Feb. 2009, pp. 370–371. • 2009

Modeling and Analysis of High-Speed I/O Links

IEEE Transactions on Advanced Packaging • 2009

Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example

R. Sredojevic, V. Stojanovic
Proc. IEEE/ACM ICCAD, Nov. 2008, pp. 314–321. • 2008

Similar Papers

Loading similar papers…