A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links

@article{Tomkins2008AZ6,
  title={A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links},
  author={Alexander Tomkins and Ricardo Andres Aroca and Takuji Yamamoto and Sean T. Nicolson and Yoshiyasu Doi and Sorin P. Voinigescu},
  journal={2008 IEEE Custom Integrated Circuits Conference},
  year={2008},
  pages={471-474}
}
This paper presents a 1.2 V 60 GHz zero-IF transceiver fabricated in a 65 nm CMOS process with a digital back-end. The chip includes a receiver with 14.7 dB gain, a low 5.6 dB noise figure, a 60 GHz LO distribution tree, a 64 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 3.5 Gb/s. The chip consumes 374 mW (232 mW) from 1.2 V (1.0 V) and occupies 1.28 times 0.81 mm2. The transceiver was characterized over temperature up to… CONTINUE READING
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