A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration

  • Minas Dasygenis
  • Published 2014 in
    2014 9th IEEE International Conference on Design…


Design space exploration of new circuit methodologies require the creation of models in hardware description languages to evaluate the characteristics for different parameters, a time consuming process. To alleviate the burden of HDL construction, we present a compact netlist format and a web tool that creates syntactically correct VHDL files. The designer… (More)
DOI: 10.1109/DTIS.2014.6850659


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