A wafer-level-chip-size-package technique with inverted microstrip lines for mm-wave Si CMOS ICs

@article{Kawai2010AWT,
  title={A wafer-level-chip-size-package technique with inverted microstrip lines for mm-wave Si CMOS ICs},
  author={Yasufumi Kawai and Shinji Ujita and Takeshi Fukuda and Hiroyuki Sakai and Tetsuzo Ueda and Tsuyoshi Tanaka},
  journal={2010 Asia-Pacific Microwave Conference},
  year={2010},
  pages={1841-1844}
}
We present a novel wafer-level-chip-size-package (WLCSP) technique with inverted microstrip line (IMSL) for mm-wave Si-CMOS ICs. The IMSL consists of a signal transmission line formed as a part of the CMOS processing and Cu-plated ground plane, where thick low-k PBO (poly-benzoxazole) is formed between them. The chip can be flip-chip bonded onto the circuit board, and the RF performance is not affected by the conditions of the assembly. Note that the use of Si-substrates with the resistivity of… CONTINUE READING

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