A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 /spl mu/m 3.5 nm Tox 1.8 V CMOS technology

@article{Sanchez1999AV3,
  title={A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 /spl mu/m 3.5 nm Tox 1.8 V CMOS technology},
  author={Higinio Sanchez and Jon Siegel and Carmine Nicoletta and Joaqu{\'i}n {\'A}lvarez and Jim Nissen and Gianfranco Gerosa},
  journal={1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)},
  year={1999},
  pages={276-277}
}
The continued scaling of transistor performance is delivering unprecedented microprocessor performance. However, the logic supply voltage, Vdd, is being reduced at a faster rate than the required I/O voltage level, OVDD. OVDD scales more slowly due to peripherals, which are built on mature technologies that require higher OVDD. Time-to-market constraints and chip integration issues further impose a single I/O driver as the desired solution. The I/O driver must meet the reliability constraints… CONTINUE READING

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References

Publications referenced by this paper.

A 450MHz PowerPC TM Microprocessor with Enhanced Instruction Set and Copper Interconnect,

J. Alvarez et al
  • 1999