A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks

@article{Tadros2014AVT,
  title={A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks},
  author={Ramy N. Tadros and Abdelrahman H. Elsayed and Maged Ghoneima and Yehea I. Ismail},
  journal={2014 IEEE International Symposium on Circuits and Systems (ISCAS)},
  year={2014},
  pages={1520-1523}
}
This paper presents a variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers. The proposed design generates the 3-level signal without a ½VDD driver, thus removing all the overhead and hassle of an additional supply. Moreover, the proposed all-digital scheme uses half the clock frequency while maintaining the same data rate of the conventional scheme. As a result, the proposed design is much more robust across all possible variations… CONTINUE READING