A unified signal transition graph model for asynchronous control circuit synthesis

  title={A unified signal transition graph model for asynchronous control circuit synthesis},
  author={Alexandre Yakovlev and Luciano Lavagno and Alberto L. Sangiovanni-Vincentelli},
  journal={Formal Methods in System Design},
Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis and specification models, but lacks a unified framework to verify directly if the circuit specification admits a correct implementation under these hypotheses.Our aim is to fill exactly this gap… 
1 Citations
Logic synthesis for asynchronous circuits based on Petri net unfoldings and incremental SAT
  • V. Khomenko, M. Koutny, A. Yakovlev
  • Computer Science
    Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004.
  • 2004
This paper proposes an efficient algorithm for logic synthesis based on the incremental Boolean satisfiability (SAT) approach and shows that this technique leads not only to huge memory savings when compared with the methods based on reachability graphs, but also to significant speedups in many cases, without affecting the quality of the solution.
Analysis and identification of speed-independent circuits on an event model
The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity based on a derivation of an event specification of the circuit behavior in a form of a signal graph.
Direct synthesis of hazard-free asynchronous circuits from STGs based on lock relation and MG-decomposition approach
A new realization algorithm is proposed to synthesize asynchronous hazard-free circuits directly from signal transition graphs (STGs) with underlying free-choice Petri nets without using state diagrams and thereby maintains problem size polynomially proportional to the number of signals.
Delay-Insensitivity and Semi-Modularity
It is proved that a circuit, with all the wire delays taken into account, is strongly delay-intensitive if and only if its behavior is quasi semi-modular.
Automatic synthesis of computation interference constraints for relative timing verification
  • Yang Xu, K. Stevens
  • Computer Science
    2009 IEEE International Conference on Computer Design
  • 2009
This paper describes an algorithm for automatic generation of RT constraints based on signal traces generated from a formal verification engine that supports relative timing constraints and is implemented in a CAD tool called Automatic Relative Timing Identifier based on Signal Traces.
Symbolic Techniques for the Automatic Test Pattern Generation for Speed-Independent Circuits
This technical report presents a novel approach to the Automatic Test Pattern Generation (ATPG) for speed-independent asynchronous circuits, based on the use of symbolic analysis techniques.
Derivation of Set and Reset Covers for gC Elements and Standard C Implementation Using STG Unfoldings
This work proposes an efficient algorithm for deriving the set and reset covers of C elements and standard C implementation based on the Incremental Boolean Satisfiability (SAT) approach and avoids constructing the state graph of an STG, and instead uses only the information about causa lity and structural conflicts between the events involved in a finite and complete prefix of its unfolding.
Structural methods for the synthesis of speed-independent circuits
Novel methods exclusively based on the structural analysis of the underlying Petri net are presented, which can be applied to any STG that can be covered by State Machines and, in particular, to all live and safe free-choice STGs.
A Design Space and its Patterns: Modelling 2phase Asynchronous Pipelines
This paper presents a complete overview of mixed 2phase linear pipeline behaviours; shows how their structuring C cuts and R cuts relate; characterise the behaviours of linear pipelines in terms of these cuts for any depth; and shows how the much larger R mixed behaviour patterns can be calculated from knowledge of the C behaviour patterns.
Research on the Key Technologies of Asynchronous Circuit Design Based on Petri Net
This paper uses Petri net method which can describe the behavior of circuits in low-level, including sequential information and describe concurrent behavior clearly, and shows that it can design the asynchronous circuit efficiently.