A unified signal transition graph model for asynchronous control circuit synthesis

@article{Yakovlev1992AUS,
  title={A unified signal transition graph model for asynchronous control circuit synthesis},
  author={Alexandre Yakovlev and Luciano Lavagno and Alberto L. Sangiovanni-Vincentelli},
  journal={Formal Methods in System Design},
  year={1992},
  volume={9},
  pages={139-188}
}
Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis and specification models, but lacks a unified framework to verify directly if the circuit specification admits a correct implementation under these hypotheses.Our aim is to fill exactly this gap… 
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