A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

@inproceedings{Chuang1993AUA,
  title={A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area},
  author={Weitong Chuang and Sachin S. Sapatnekar and Ibrahim N. Hajj},
  booktitle={ICCAD},
  year={1993}
}
This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period speci cation under the standard-cell paradigm. This is e ected by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual ipops. Traditional methods treat these two problems separately, which may lead to very sub-optimal solutions in some cases. Experimental… CONTINUE READING

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