A tutorial on CRC computations

@article{Ramabadran1988ATO,
  title={A tutorial on CRC computations},
  author={Tenkasi V. Ramabadran and Sunil S. Gaitonde},
  journal={IEEE Micro},
  year={1988},
  volume={8},
  pages={62-75}
}
The theory of cyclic redundancy codes (CRS) is reviewed. Four software algorithms for performing CRC computations are described: table lookup, reduced table lookup, on-the-fly, and wordwise. They are compared in terms of their speeds and storage requirements.<<ETX>> 
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References

SHOWING 1-3 OF 3 REFERENCES
Cyclic Codes for Error Detection
TLDR
The potentialities of these codes for error detection and the equipment required for implementing error detection systems using cyclic codes are described in detail. Expand
Byte-Wise CRC Calculations
TLDR
A cyclic redundancy code can be calculated on bytes instead of bits to reduce calculation time by a factor of almost four. Expand
An Efficient Software Method for Implementing Polynomial Error Detection Codes