A tunnel FET compact model including non-idealities with verilog implementation

@article{Sajjad2018ATF,
  title={A tunnel FET compact model including non-idealities with verilog implementation},
  author={Redwan Noor Sajjad and Ujwal Radhakrishna and Dimitri A. Antoniadis},
  journal={Solid-State Electronics},
  year={2018}
}
Abstract We present a compact model for Tunnel Field Effect Transistors (TFET), that captures several non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps ( D it ), along with Verilog-A implementation. We show that the TAT, together with band edge non-abruptness known as the Urbach tail, sets the lower limit of the sub-threshold swing and the leakage current at a given temperature. Presence of charged trap states also contributes to reduced gate efficiency… 
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