A threshold voltage controlling circuit for short channel MOS integrated circuits

  title={A threshold voltage controlling circuit for short channel MOS integrated circuits},
  author={M. Kubo and R. Hori and O. Minato and K. Sato},
  journal={1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  • M. Kubo, R. Hori, +1 author K. Sato
  • Published 1976
  • Materials Science
  • 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
A threshold stabilizing circuit which controls substrate of short channel (2 μm) MOS-ICs by negative-feedback, will be described. Operating range of VDD(1.5 to 8V) is free from threshold fluctuations. 

Figures from this paper

Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation
  • T. Kobayashi, T. Sakurai
  • Materials Science
  • Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94
  • 1994
A circuit technique to reduce threshold voltage fluctuation by a use of self-substrate-bias is introduced. The substrate bias is controlled so that leakage current of a representative MOSFET isExpand
In sub-micron CMOS design, non-minimum length transistors offer the possibility of achieving excellent leakage control without the disadvantages of other known leakage control techniques. PreliminaryExpand
The Application of Transistor Technology to Computers
Four primary computer technology areas that have helped bring about this advance and which have significantly changed the nature of computer components are discussed: FET logic, FET memory, bipolar logic, and bipolar memory. Expand
A Historical Review of Low-Power, Low-Voltage Digital MOS Circuits Development
  • K. Itoh
  • Computer Science
  • IEEE Solid-State Circuits Magazine
  • 2013
This article reviews digital MOS circuits as they have been developed over the last 50 years, since the advent of integrated circuits (ICs). Expand
Low-Voltage Embedded-RAM Technology: Present and Future
A perspective is given with emphasis on needs for simple/high signal-to-noise ratio memory cells with a pure logic compatible process, high-speed subthreshold-current reduction focusing on active mode, and memory-rich SoC architectures. Expand
A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias
Substrate bias is continuously controlled from -1.5 V (backward bias) to 0.5 V (forward bias) to compensate for fabrication fluctuation, supply voltage variation, and operating temperature variation.Expand
Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS
Simulations show that by increasing gate lengths to 200 nm instead of the minimum 60 nm, may increase the footprint area of logic gates by only 12 %, while at the same time reducing probability of failure by up to several orders of magnitude. Expand
Review and future prospects of low-voltage RAM circuits
This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standbyExpand
A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement
The maximum output current was improved by 240% as compared to the conventional charge pump design using only the forward body bias, and the low-power adaptive dead-time (AD) circuit is used. Expand
CMOS/SOS memory circuits for radiation environments
The CMOS/SOS circuits discussed in this paper are key elements for radiation-hardened memory designs with state-of-the-art LSI density and performance. Expand