A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders

@inproceedings{Dimitrakopoulos2003ASM,
  title={A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders},
  author={Giorgos Dimitrakopoulos and Haridimos T. Vergos and Dimitris Nikolos and Costas Efstathiou},
  booktitle={ISCAS},
  year={2003}
}
In this paper a systematic methodology for designing parallelprefix modulo 2 − 1 adders, for every n, is introduced. The resulting modulo 2 − 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims to the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area×time complexity reduction of up to 46% when compared to… CONTINUE READING
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