A system for automated built-in self-test of embedded memory cores in system-on-chip

@article{Garimella2005ASF,
  title={A system for automated built-in self-test of embedded memory cores in system-on-chip},
  author={Subhadra Garimella and Charles E. Stroud},
  journal={Proceedings of the Thirty-Seventh Southeastern Symposium on System Theory, 2005. SSST '05.},
  year={2005},
  pages={50-54}
}
A system for automatic generation of built-in self-test (BIST) for embedded memory cores in a system-on-chip (SoC) is presented. The BIST approach tests RAMs of any address and data bus widths and can test both single-port and dual-port RAMs operating in synchronous or asynchronous mode. A field programmable gate array (FPGA) independent BIST model is developed using VHDL. The parameterized VHDL model has been synthesized and used to test various sizes and types of embedded RAMs in SoCs and… CONTINUE READING

From This Paper

Figures, tables, results, connections, and topics extracted from this paper.
5 Extracted Citations
3 Extracted References
Similar Papers

Citing Papers

Publications influenced by this paper.

Similar Papers

Loading similar papers…