A system architecture solution for unreliable nanoelectronic devices

  title={A system architecture solution for unreliable nanoelectronic devices},
  author={Jie Han and P. Jonker},
The shrinking of electronic devices will inevitably introduce a growing number of defects and even make these devices more sensitive to external influences. It is, therefore, likely that the emerging nanometer-scale devices will eventually suffer from more errors than classical silicon devices in large scale integrated circuits. In order to make systems based on nanometer-scale devices reliable, the design of fault-tolerant architectures will be necessary. Initiated by von Neumann, the NAND… Expand

Figures from this paper

A Cache Architecture for Extremely Unreliable Nanotechnologies
A novel Content Addressable Memory-based design incorporating "best practice" fault tolerant design techniques is proposed, which requires 15 times the number of devices but enables the use of device technologies with defect rates higher than 10-6, a three order of magnitude improvement over non-fault tolerant designs. Expand
Reliability evaluation of von Neumann multiplexing based defect-tolerant majority circuits
The results in this paper show that majority circuits when multiplexed using von Neumann's technique admits lesser reliability at the same level of redundancy for small gate failure probability than in the case of NAND gates, and higher reliability of computation when large gate failure probabilities are considered. Expand
Fault Tolerance Issues in Nanoelectronics
Estimates are given for the redundancy level to be provided on nanochips, so as to make their mean time between failures acceptable, and it is found that, for logic chips, space redundancies up to a few tens are required, if mean times between failures have to be of the order of a few years. Expand
Tools and techniques for evaluating reliability of defect-tolerant nano architectures
  • D. Bhaduri, S. Shukla
  • Computer Science
  • 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541)
  • 2004
Different tools and techniques are developed that can evaluate the reliability measures of combinational logic blocks, and can be used to analyze trade-offs between reliability and redundancy for different architectural configurations, including a Matlab based tool called Nanolab and a probabilistic model checking based tool named Nanoprism. Expand
A defect-?and fault-tolerant architecture for nanocomputers
Both von Neumann's NAND multiplexing, based on a massive duplication of imperfect devices and randomized imperfect interconnects, and reconfigurable architectures have been investigated to come upExpand
NANOLAB-a tool for evaluating reliability of defect-tolerant nanoarchitectures
This paper has developed MATLAB-based libraries for fundamental logic gates that can compute probability distributions and entropies at the outputs for specified discrete input distributions and in the presence of noise at the inputs and interconnects, and automates the evaluation of reliability measures of combinational logic blocks. Expand
Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy
This paper presents a fault-tolerant nanoscale architecture based on the implementation of logic systems with Averaging Cells Linear Threshold Gates (AC-LTGs), and shows that the AC-LTG is a valuable alternative in specific nanoscales conditions. Expand
Tools and techniques for evaluating reliability trade-offs for NANO-architectures
Different analytical and automation methodologies that can evaluate the reliability measures of combinational logic blocks, and can be used to analyze trade-offs between reliability and redundancy for different architectural configurations are discussed. Expand
Variability-aware architectures based on hardware redundancy for nanoscale reliable computation
During the last decades, human beings have experienced a significant enhancement in the quality of life thanks in large part to the fast evolution of Integrated Circuits (IC). This unprecedentedExpand
Fault and Defect Tolerant Computer Architectures: Reliable Computing with Unreliable Devices
As conventional silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology continues to shrink, logic circuits are increasingly subject to errors induced by electrical noise and cosmicExpand


Architectures for reliable computing with unreliable nanodevices
As electronic devices get smaller and smaller, so the probability of errors in manufacturing increases, and the need to use fault-tolerant techniques. This paper compares the relative performance ofExpand
Single-electron devices and their applications
The goal of this paper is to review in brief the basic physics of single-election devices, as well as their-current and prospective applications. These devices based on the controllable transfer ofExpand
A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology
The defect-tolerant architecture of Teramac, which incorporates a high communication bandwith that enables it to easily route around defects, has significant implications for any future nanometer-scale computational paradigm. Expand
The use of nanoelectronic devices in highly parallel computing systems
Simulated results are presented which indicate that improvements in clock rates and packing density over the best current systems should be attainable, over the class of data-parallel computers. Expand
Toward robust integrated circuits: The embryonics approach
The ongoing research efforts to meet three challenges are described, that of implementing the original specifications formulated by John von Neumann for the conception of a self-replicating automaton, and that of attempting to show that the microscopic architectures of artificial and natural organisms, i.e., their genomes, share common properties. Expand
Invariance of complexity measures for networks with unreliable gates
A new probabilistic failure model for networks of gates is formulated and supports the proofs of both the positive and negative results appearing in the literature. Expand
Reliable computation by networks in the presence of noise
  • T. Feder
  • Computer Science
  • IEEE Trans. Inf. Theory
  • 1989
Lower bounds on the depth of Boolean networks that can compute reliably in the presence of randomly occurring failures are proved. A bound is also given on the reliability that error-tolerantExpand
On a lower bound for the redundancy of reliable networks with noisy gates
A proof is provided that a logarithmic redundancy factor is necessary for the reliable computation of the parity function by means of a network with noisy gates. This result was first stated by R.L.Expand
On networks of noisy gates
  • N. Pippenger
  • Mathematics, Computer Science
  • 26th Annual Symposium on Foundations of Computer Science (sfcs 1985)
  • 1985
We show that many Boolean functions (including, in a certain sense, "almost all" Boolean functions) have the property that the number of noisy gates needed to compute them differs from the number ofExpand
Programmable logic using a SET electron box
  • R. H. Klunder, J. Hoekstra
  • Computer Science
  • ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)
  • 2001
This paper shows how the, single electron tunneling (SET), electron box can be used as a programmable logic subcircuit. The digital functions NAND, NOR, and inverter made with this subcircuit areExpand