A survey on digital background calibration of ADCs

  title={A survey on digital background calibration of ADCs},
  author={Antonio J. Gin{\'e}s and Eduardo J. Peral{\'i}as and Adoraci{\'o}n Rueda},
  journal={2009 European Conference on Circuit Theory and Design},
In this paper, a general description of digital ADC calibration approaches in current state-of-the-art is presented, with particular emphasis in Pipeline converters. The study performs a classification of the existing techniques considering two basic aspects: a) the principle of operation and the particular errors which can be compensated after calibration, b) the process from which a measurement of the errors, and therefore the calibrated output code, is obtained. Attention will be paid to… CONTINUE READING


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Showing 1-10 of 34 references

A Low-Power 14-b 5 MS/s CMOS Pipeline ADC with Background Analog Self-Calibration

J. Goes
IEEE Eu. Solid-State Cir. Conf., Sep. 2000, pp. 364-367. • 2000
View 10 Excerpts
Highly Influenced

Gain Error Correction in Pipeline ADCs with Digital Redundancy

A. J. Ginés
IEEJ International Analog VLSI Workshop, Oct. 2004, pp. 155-160. • 2004
View 5 Excerpts
Highly Influenced

A digital background calibration technique for time-interleaved ADCs

D. Fu
IEEE J. of Solid-State Circuits, Dec. 1998, pp. 1904-1911. • 1998
View 5 Excerpts
Highly Influenced

A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers • 2008
View 1 Excerpt

Improved Background Algorithms for Pipeline ADC Full Calibration

2007 IEEE International Symposium on Circuits and Systems • 2007
View 1 Excerpt

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