A suitable FPGA implementation of floating-point matrix inversion based on Gauss-Jordan elimination

@article{AriasGarcia2011ASF,
  title={A suitable FPGA implementation of floating-point matrix inversion based on Gauss-Jordan elimination},
  author={Janier Arias-Garcia and Ricardo Pezzuol Jacobi and Carlos H. Llanos and Mauricio Ayala-Rinc{\'o}n},
  journal={2011 VII Southern Conference on Programmable Logic (SPL)},
  year={2011},
  pages={263-268}
}
This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA with single-precision floating-point representation, whose main unit is the processing component for Gauss-Jordan elimination. This component consists of other smaller arithmetic units, organized to maintain the accuracy of the results without the need to internally normalize and de-normalize the floating-point data. The implementation of the operations and the whole unit take advantage of the… CONTINUE READING
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