A study of digital decoders in flash analog-to-digital converters

  title={A study of digital decoders in flash analog-to-digital converters},
  author={Erik Sall and Mark Vesterbacka and K. Ola Andersson},
  journal={2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)},
Digital decoders in flash analog-to-digital converters are studied. An attractive approach for realizing the decoder is to count the ones in the thermometer coded comparator output with, e.g. a Wallace tree. Such an ones-counter can be fast and it incorporates global bubble error correction. We also suggest an improvement of the Wallace tree decoder, obtained by applying folding. This yields a decoder with less area and a circuit with shorter critical path, which should make it possible to… CONTINUE READING
Highly Cited
This paper has 61 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 17 citations

62 Citations

Citations per Year
Semantic Scholar estimates that this publication has 62 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-8 of 8 references

New Encoding Scheme For High-Speed Flash ADC’s

  • F. Kaess, R. Kanan, B. Hochet, M. Declercq
  • IEEE Proc. Circuits and Syst., vol. 1, pp. 5-8…
  • 1997
Highly Influential
14 Excerpts

A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction

  • K. Uyttenhove, M. Steyaert
  • IEEE Proc. Custom Integrated Circuits Conference…
  • 2000
Highly Influential
4 Excerpts

8-mW, 1-V, 100-MSPS, 6-BIT A/D Converter Using A Transconductance Latched Comparator

  • J. Terada, Y. Matsuya, F. Morisawa, Y. Kado
  • Proc. IEEE Asia Pacific Conf. on ASICs, .
  • 2000
2 Excerpts

Design of high - speed low - power 3 - 2 counter and 4 - 2 compressor for fast multipli

  • M-R Jiang S-F Hsiao
  • Digital Integrated Circuits : A Design…