A stereo multi-bit /spl Sigma//spl Delta/ D/A with asynchronous master-clock interface

Abstract

An oversampling DAC that generates low-jitter, synchronous and oversampled clock internally uses an on-chip digital phase-locked loop (DPLL) and a digital sample-rate converter to decouple the DAC conversion rate from the audio sample rate. This allows the DAC to be driven by an independent low-jitter clock source that minimizes jitter-induced amplitude… (More)

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