A stacked memory device on logic 3D technology for ultra-high-density data storage

  title={A stacked memory device on logic 3D technology for ultra-high-density data storage},
  author={Jiyoung Kim and Augustin Hong and Sung Min Kim and Kyeong-Sik Shin and Emil B. Song and Yongha Hwang and Faxian Xiu and Kosmas Galatsis and Chi On Chui and Rob N. Candler and Siyoung Choi and Joo-tae Moon and Kang L. Wang},
We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices… 

Enhancement of the electrical characteristics for vertical NAND flash memory devices using a modified array structure

The electrical characteristics of vertical NAND flash memory devices with a modified structure were investigated by using a technology computer-aided design simulation tool in order to reduce the

MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube

This paper proposes MEG, an open-source, configurable, cycle-exact, and RISC-V based full system simulation infrastructure using FPGA and HMC, and provides a prototype implementation of MEG on Xilinx VCU110 board and demonstrates its capability, fidelity, and flexibility on real-world benchmark applications.


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The next generation mass storage devices – Physical principles and current status

The physical principles of these emerging storage technologies and their superiorities as the next generation data storage device, as well as their respective technical challenges on further enhancing the storage capacity are reviewed.

A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The

Electrical memory devices based on inorganic/organic nanocomposites

Tae Whan Kim and co-workers review how nanocomposite materials that combine organic and inorganic materials are attractive for use in memory components. A wide variety of structures have been used to

3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory

3D-FlashMap permutes the physical mapping of blocks and maximizes the distance between consecutively logical blocks, which can significantly reduce the disturbance to adjacent physical pages and effectively enhance the reliability of 3D flash memory.

Physical principles and current status of emerging non-volatile solid state memories

The physical principles of flash memories and their technical challenges that affect the ability to enhance the storage capacity are reviewed, and a detailed discussion of novel technologies that can extend the storage density offlash memories beyond the commonly accepted limits are presented.

Interface engineering of 9X stacked 3D NAND flash memory using hydrogen post-treatment annealing

This study investigates the effects of hydrogen post-treatment on 3D NAND flash memory. Hydrogen post-treatment annealing (PTA) is suggested to passivate the defects in the tunneling oxide/poly-Si

Accelerating Sub-Block Erase in 3D NAND Flash Memory

The main idea of SpeedupGC is to guide the hotly-updated data to the blocks that are about to be erased, so as to speculatively produce more invalid pages and suppress the relocation overhead.



Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node

For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The

Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

A 3-D flash memory cell of VRAT has been fabricated using a unique and simple3-D integration method of PIPE (planarized integration on the same plane), which allows for the successful implementation of ultra high density flash memory.

Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

SiN-based gate dielectrics for the consistency with the 'gate-first' process which is unique to BiCS flash technology, and 'macaroni' body FETs for better controllability over the sub-threshold characteristics of depletion-mode poly-silicon transistors are adopted.

Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices

We propose pipe-shaped bit cost scalable (P-BiCS) flash memory which consists of pipe-shaped NAND strings folded like a u-shape instead of the straight-shape. P-BiCS flash technology achieves a

Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)

A novel 3-D NAND flash memory device, VSAT (Vertical-Stacked-Array-Transistor), has successfully been achieved. The VSAT was realized through a cost-effective and straightforward process called PIPE

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous

8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

  • Jong-Ho ParkS. Hur B. Ryu
  • Engineering
    IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
  • 2004
For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 /spl mu/m/sup 2/, the smallest ever

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.

Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 μm2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies

A novel high-density 5F/sup 2/ NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories

This paper describes a novel high density 5F/sup 2/ (F: feature size) NAND STI cell technology which has been developed for a low bit-cost flash memories. The extremely small cell size of 0.31 /spl