A speed oriented fully automatic layout program for random logic VLSI devices

  title={A speed oriented fully automatic layout program for random logic VLSI devices},
  author={A. Feller and R. Noto},
  booktitle={AFIPS National Computer Conference},
  • A. Feller, R. Noto
  • Published in
    AFIPS National Computer…
  • Computer Science
  • This paper describes a low cost, quick turnaround capability for generating high performance, random logic LSI and VLSI devices using the Standard Cell approach. This standard cell approach, described below, utilizes a fully automatic layout capability that automatically maximizes the speed of logic paths identified by the user as critical. In spite of the sophistication and size of the automatic layout program, the system can be run on Midicomputer based systems as well as time shared Main… CONTINUE READING
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