A speed oriented fully automatic layout program for random logic VLSI devices

@inproceedings{Feller1978ASO,
  title={A speed oriented fully automatic layout program for random logic VLSI devices},
  author={A. Feller and R. Noto},
  booktitle={AFIPS National Computer Conference},
  year={1978}
}
  • A. Feller, R. Noto
  • Published in
    AFIPS National Computer…
    1978
  • Computer Science
  • This paper describes a low cost, quick turnaround capability for generating high performance, random logic LSI and VLSI devices using the Standard Cell approach. This standard cell approach, described below, utilizes a fully automatic layout capability that automatically maximizes the speed of logic paths identified by the user as critical. In spite of the sophistication and size of the automatic layout program, the system can be run on Midicomputer based systems as well as time shared Main… CONTINUE READING
    16 Citations

    Figures, Tables, and Topics from this paper

    Techniques for area estimation of VLSI layouts
    • 117
    APSS: An Automatic PLA Synthesis System
    • 2
    PLEST: A Program for Area Estimation of VLSI Integrated Circuits
    • 12
    A Hierarchy-Driven Amalgamation of Standard and Macro Cells
    • E. Reingold, K. Supowit
    • Engineering, Computer Science
    • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    • 1984
    • 3
    The Evolution of Design Automation to Meet the Challanges of VLSI
    • 10
    • PDF
    The Benefits of External Wires in Single Row Routing
    • 1
    Maximizing pin alignment in semi-custom chip circuit layout
    • 5
    A mixed mode placement algorithm for combined design of macro blocks and standard cells
    • 6